One type of RNG uses a positive edge-triggered D-type flip-flop with a high frequency nominally 50 percent duty cycle square wave applied to the data input terminal and a low frequency square wave having cycle-to-cycle jitter which spans two full cycles of the high frequency wave applied to the clock input terminal. The random number is generated at the Q output terminal of the flip-flop. If the duty cycle is not exactly 50 percent, then the number generated is biased. If the jitter does not span two full cycles, there is bit-to-bit correlation in the output number. With either of these two conditions, a given bit can be determined with better than a 50 percent probability. Coupling of adjacent output signals of the flip-flop to a two-input exclusive-OR gate improves the randomness of the number generated if the duty cycle of the data waveform is different than 50 percent, but does not compensate for insufficient jitter in the clock waveform.
It is desirable to have a RNG which uses a positive edge-triggered D-type flip-flop with high and low frequency input signals which compensates for both duty cycle and jitter variations.